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Chapter 9 The Processor Part 2
Friday, 16 December 2016 • 00:59 • 0 comments



PIPELINING ANALOGY

 Pipelined laundry: overlapping execution

  • Parrellalism improves performance
FOUR LOAD


  • Speedup = 8 / 3.5 = 2.3


NON-STOP


  • Speedup 
= 2n / 0.5n + 1.5 = 4 number of stages

MIPS PIPELINE


PIPELINE SPEEDUP

IF ALL STAGES BALANCED
Time between instructions = Time between instructions   (pipelined)
                                                     Number of stages           (non-pipelined)

IF NOT BALANCED
Speedup is less

HAZARD

  • Situation that prevent starting the next instruction in the next cycle
  • 3 Types of HAZARD :
1. Stucture Hazard
A required recource is busy

2. Data Hazard
Need to wait for previous instruction to complete its data read/write

3. Control Hazard
Deciding on control action depend on previous instruction



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