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Chapter 5: The Basic of Logic Design
Thursday 27 October 2016 • 06:24 • 0 comments



Karnaugh Map & Simplification of Combinational Circuit 

This video will show you guys on how to build a K-Map, filling out a K-Map and will explain on how to obtain the most simplified Boolean expressions.
  


Introduction of Multimedia Logic

  1. Adder
  • Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

Block Diagram of Half Adder

Truth Table

Half Adder Truth Table

Circuit Diagram

Half Adder Circuit Diagram
  • Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.

Block diagram

Block Diagram of Full Adder

Truth Table

Full Adder Truth Table

Circuit Diagram

Full Adder Circuit Diagram
2. Multiplexer 

Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal that means it will perform the required operation when it is low.

Block diagram

Block Diagram of n:1 Multiplexer
Multiplexers come in multiple variations
  • 2 : 1 multiplexer
  • 4 : 1 multiplexer
  • 16 : 1 multiplexer
  • 32 : 1 multiplexer

Block Diagram

2:1 Multiplexer Block Diagram

Truth Table

2:1 Multiplexer Truth Table
3. Decoder

A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.

Block diagram

Block Diagram of Decoder
Examples of Decoders are following.
  • Code converters
  • BCD to seven segment decoders
  • Nixie tube decoders
  • Relay actuator

2 to 4 Line Decoder

The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific combination of inputs.

Block diagram

Block Diagram of 2 to 4 Decoder

Truth Table

Truth Table of 2 to 4 Decoder

Logic Circuit

Logic Circuit of 2 to 4 Decoder
4. SR Flip Flop
 
It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.

Block Diagram

Block Diagram of SR Flip Flop

Circuit Diagram

Circuit Diagram of SR Flip Flop

Truth Table

Truth Table of SR Flip Flop

Operation

S.N.ConditionOperation
1S = R = 0 : No change
If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs.
2S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
3S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition.
4S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND latch.




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